The present invention relates to a vector processing system and, more particularly, to a vector processing system using firmware control.
Conventionally, processing systems equipped with vector processing instructions for executing the same processing on a large quantity of vector data, such as the one disclosed in U.S. Pat. No. 4,620,275, are used in many cases as means for faster scientific or technological calculation.
In so-called supercomputers, vector processing instructions are often executed with a specialized circuit for vector processing. Meanwhile, in systems in which performance requirements are not so stringent as on supercomputers, vector processing instructions are frequently executed by the common use of a processing unit for usual scalar processing with a view to restraining the expansion of hardware quantity.
A processing unit for use in scalar processing usually has no pipeline architecture. Therefore, as long as a vector element is being processed, processing of the next element cannot be started. In a vector processing system where the execution of the processing of each vector element is achieved under hardware control and the command to start the processing of each element is given under firmware control, the command to start processing a given element is issued after the processing of the preceding element has been judged to have been completed.
Meanwhile, the time taken to execute floating point processing in such a system often varies with whether or not normalization of the result of processing is required. For an example of such a system, reference may be made to U.S. Pat. No. 4,589,067.
Said judgement of the completion of previous processing in order to give a starting command under firmware control requires branch judgement, according to a completion signal fed from the processing circuit, as to whether or not the processing of the next element is to be started. Where a branch of firmware is to be executed, the process of receiving the completion signal, reading out a microinstruction from a control memory and executing it constitutes an important factor determining the machine clock. Therefore, in the conventional vector processing system described above, various control actions are done from the time the processing of one vector element is completed until the time that of the next is started, resulting in the disadvantage that time is wasted such as in the reading of the microinstruction from the control memory and a consequent delay in the execution of the microinstruction.